In automotive applications the use of Direct Current (DC) or Brushless DC (BLDC) motors for fan, pump or actuator applications is very common with the trend of replacing the traditional DC with BLDC motors. In most automotive applications, detection of fault conditions of the BLDC motor and the control electronics is mandatory. For this reason, the control electronics should be able to identify a possible fault condition and then apply counter measures, e.g., in order to protect the system. Often the detected fault condition is reported to a system controller and may be accessible via the diagnosis interface of the automobile for further service investigations.
As disclosed, e.g., in document IT102016000009376, a motor is often driven using one or more half-bridges as a function of one or more respective PWM signals.
For example, FIG. 1 shows a typical half-bridge arrangement 20 comprising two electronic switches SW1 and SW2, such as n-channel power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistor), connected in series between a supply voltage Vdd and a ground GND.
Usually, the switches SW1 and SW2 are closed alternatively in order to connect the output OUT of the half-bridge arrangement 20, i.e., the intermediate point between the switches SW1 and SW2, either to the voltage Vdd or to ground GND.
For this purpose, the half-bridge is driven as a function of two drive signals DRV1 and DRV2, which are connected (e.g., directly) to the control gates of the switches SW1 and SW2, respectively.
Specifically, in order to correctly drive the control gates, usually a high-side driver 2001 is used to generate the drive signal DRV1 for the high-side switch SW1 as a function of a first control signal IN1, and a low-side driver 2002 is used to generate the drive signal DRV2 for the low-side switch SW2 as a function of a control signal IN2.
The control signal IN2 corresponds often to an inverted version of the signal IN1 (or vice versa), i.e., the signal IN2 is low when the signal IN1 is high and vice versa. For example, in FIG. 1 is used an inverter 202 which receives at input the signal IN1 and provides at output the signal IN2.
The output OUT of the half-bridge arrangement 20 may be used to drive a load. For example, in FIG. 1, the half-bridge arrangement 20 drives a motor M1 connected between the output OUT of the half-bridge arrangement 20 and ground GND.
Conversely, FIG. 2 shows an example in which two half-bridge arrangements 20a and 20b are used to drive a linear motor M2, such as a voice coil motor, connected between the output OUTa of the first bridge arrangement 20a and the output OUTb of the second bridge arrangement 20b. As well known to those of skill in the art, in this case, also the rotation direction of the motor M2 may be controlled by applying appropriate control signals INa and INb to the half-bridge arrangements 20a and 20b.
Finally, FIG. 3 shows an example in which three half-bridge arrangements 20a, 20b and 20c are used to drive a three phase motor M3, such as a spindle motor, connected between the outputs OUTa, OUTb and OUTc of the half-bridge arrangements 20a, 20b and 20c.
As mentioned before, the control signals may be PWM signals, i.e., signals with a fixed frequency and a variably duty cycle. For example, document IT102015000046790 discloses a solution for generating two PWM signals which may be used, e.g., for generating the signals INa and INb in the solution shown in FIG. 2.
FIG. 4 shows in this regards a typical PWM signal PWM, such as the signal IN, corresponding to a pulsed signal comprising a single pulse P for each switching cycle with duration or period TPWM, wherein the switch-on duration TON of the pulse P may be variable as a function of a control signal.
Generally, the pulse P is not necessarily at the beginning of each switching cycle, but each switching cycle may comprise an initial switch-off period TOFF1 before the pulse P and a final switch-off period TOFF2 after the pulse P, with:TPWM=TOFF1+TON+TOFF2  (1)with the switch-off duration TOFF being:TOFF=TOFF1+TOFF2  (2)wherein the duty cycle D of each switching cycle is given by:D=TON/TPWM  (3)
Accordingly, e.g., for an advanced automotive application, the diagnoses of control electronics should include a detection circuit configured to detect PWM hardware failures.
FIGS. 5a and 5b shows typical PWM hardware failures. Specifically, FIG. 5a shows the desired or requested PWM signal PWMR comprising four pulses P1-P4 and FIG. 5b shows the generated signal PWM. In the example considered, the third pulse P3 has a different duty cycle and the fourth pulse P4 is missing.
In order to detect such PWM failures, two known solutions can be used.
FIG. 6 shows the first solution, wherein a redundancy control is performed.
Specifically, in the example considered, a first PWM signal generator 301 is used to generate a first PWM signal PWM1, such as the signals IN described with respect to FIGS. 1 to 3, which may be used to drive a half-bridge arrangement 20.
The circuit comprises moreover a second PWM signal generator 302 configured to generate a second PWM signal PWM2, wherein both PWM signal generators 301 and 302 are redundant, i.e., use the same configuration and thus should generate the same PWM signals.
In the example considered, an additional redundancy control checking unit 32, often in the form of a dedicated hardware module, is used to verify whether the signals PWM1 and PWM2 correspond, and possibly generates a failure signal FS when a mismatch is detected.
Conversely FIG. 7 shows the second solution. In this case a single PWM signal generator 30 is used to generate a PWM signal PWM.
In the example considered, the signal PWM is provided to a read-back module 34, often in the form of a dedicated hardware module, which determines the characteristics of the PWM signal, such as the switching period TPWM and the switch-on time TON.
These characteristics are provided to a further module 36, such as a software module, which verifies whether the characteristics requested correspond to the generated characteristics provided by the read-back module 34, and possibly generates a failure signal FS when a mismatch is detected.
The above solutions are described, e.g., in the application note AN4266—“Safety application guide for SPC56xL70xx family”, STMicroelectronics, September 2013.